This invention relates to programmable logic device (“PLD”) integrated circuits, and more particularly to high-speed serial interface (“HSSI”) circuitry for use on PLDs.
It is increasingly common for PLDs to include HSSI circuitry for use in enabling the PLD to receive and/or transmit high-speed serial data signals from or to other devices in a system that includes the PLD. On the receiver side, such HSSI circuitry may begin with (or include at an early point or stage) some automatic or adaptive equalization capability or circuitry. Such “front end” equalization capability helps to improve the condition of the received serial data signal so that it can be more accurately interpreted by subsequent circuitry on the PLD. Among the possible objectives of such equalization circuitry may be to sharpen the distinction between the two binary states of the received signal. This may include attempting to make transitions in the received signal steeper and/or stronger, and/or increasing the fraction of time that the received signal is in one or the other of its two binary states (i.e., not in transition between those states). Improving the condition of the received signal in respects such as these can improve the ability of downstream circuitry on the PLD to correctly recover clock and/or data information from the received signal, especially from received signals having high data rates and relatively low voltage swing between high and low states. Such downstream circuitry can include clock and data recovery (“CDR”) circuitry, and it is important for such circuitry to avoid inter-symbol interference (“ISI”) (i.e., inability of the circuitry to correctly distinguish each successive data bit from the adjacent bits, especially an immediately adjacent bit having a different value).
Because PLDs are typically designed to be relatively general-purpose devices, it is often not known in advance exactly what will be the characteristics of the various systems in which the PLD may be used. Signal transmission characteristics can be different in different types of systems. To enable the PLD to provide the best possible performance in any of several different systems, the PLD may be equipped with equalization circuitry of the type mentioned above that can automatically adapt its performance to best equalize the signal it receives in a particular system. The sophistication of such adaptive or automatic equalization circuitry may lead to a need or desire to test the performance of that circuitry separate from other circuitry on the PLD.